The present invention relates to a semiconductor memory device which has sub bit lines, and more particularly to a dynamic random access memory (DRAM) whose architecture is convenient in the higher integration of a memory device.
The higher integration of a DRAM has progressed rapidly. For example, the extent of integration has doubled in three years. Such higher integration of a DRAM has been realized mainly by (i) the progress of super fine processing techniques and (ii) increase of chip size. Another reason which can not be omitted is an improvement of the memory cell structure. As a matter of fact, such an improvement of the memory cell structure enables a higher integration of a DRAM than that based upon super fine processing techniques. This is clear according to the history of DRAMs. The first memory cell structure in the history is a four (4) transistor-type cell in which four (4) MOS transistors are required to hold one (1) bit of data. Thereafter, three (3) transistor-type cells emerged, and then, after the advent of the 16K bit DRAM, one (1) transistor-type cells have been mainly used to date. As is apparent from the foregoing, the higher integration of DRAM has been realized by an improvement of the memory cell structure, i.e., a reduction of the number of transistors which form a memory cell. In addition to that, in the course of development from 16K bit DRAM to a 1M bit DRAM, the high integration of a DRAM has been realized mainly by, the progress of super fine processing techniques and an improvement in the layout in memory cells. After the advent of the 1M bit DRAM, the high integration of a DRAM has been realized and will be realized by adopting a unique structure of a memory cell capacitor in which a capacitance is formed in a groove vertically formed in a silicon substrate so that the plane size of a capacitor can be minimized. That is, in this case, a size reduction of a memory cell can be realized by the three dimensionalization of a cell.
In the course of the above-stated development, there has been no substantial improvement or change as to peripheral circuits which are necessary for the DRAM and depend upon the memory cell pitch, e.g., sense amplifiers.
Under such circumstances, the higher integration of the DRAM based upon an improvement of the memory cell structure has progressed day by day. As a result, a gap between the peripheral circuits of a DRAM and the memory cell pitch has been increasing.
Therefore, in the foreseeable future, there may occur a case wherein the extent of integration of a DRAM is defined by its peripheral circuits.